The present invention relates generally to integrated circuits, and particularly, but not by way of limitation, to semiconductor memories such as a dynamic random access memory (DRAM) having a memory cell with a vertical transistor and buried word lines and body lines.
Semiconductor memories, such as dynamic random access memories (DRAMs), are widely used in computer systems for storing data. A DRAM memory cell typically includes an access field-effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. The data charges on the storage capacitor are periodically refreshed during a refresh operation.
One consideration in using such access FETs is in providing a body bias voltage to the body portion of the memory cell access FET to improve memory cell operation. The body bias voltage allows the memory cell to operate from a low power supply voltage, such as 1.5 volts, from which a gate voltage controlling the access FET is derived. Turning the access FET on to transfer data to or from the storage capacitor requires a gate voltage in excess of a turn-on threshold voltage. However, low power supply voltages, such as 1.5 volts, may not provide sufficient overdrive voltage in excess of the threshold voltage to fully turn on the access FET. The gate voltage required for turning on the access FET can be reduced by controlling the body bias voltage. When the access FET is turned off, the body bias voltage also controls a subthreshold leakage current of the access FET. The access FET is turned off during a time period when data is stored as charge on the storage capacitor. During the time period when the access FET is turned off, the subthreshold leakage current removes some of the stored data charges from the storage node of the storage capacitor. The body bias voltage value controls the threshold voltage of the access FET that is coupled to the storage node. By increasing the threshold voltage of the access FET when it is turned off, the subthreshold leakage current is reduced. Without a proper body bias voltage, the subthreshold leakage current would lead to short data retention times.
Providing the body bias voltage to the memory cell access FETs requires a conductive body line that interconnects body contacts to the access FET body regions that receive the body bias voltage. The body line, as well as bit line, word line, and other such conductors all occupy integrated circuit surface area. To increase DRAM data storage density, the surface area of each memory cell, referred to as its xe2x80x9cfootprintxe2x80x9d, must be minimized. However, conventional memory cells typically require bit, word, and body lines on the upper surface of the memory cell, requiring surface area in addition to that of the memory cell storage capacitor.
Memory density is typically limited by a minimum lithographic feature size (F) that is imposed by lithographic processes used during fabrication. For example, the present generation of high density dynamic random access memories (DRAMs), which are capable of storing 256 Megabits of data, typically require an area of 8F2 per bit of data. There is a need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs. Increasing the data storage capacity of semiconductor memories requires a reduction in the size of the access FET and storage capacitor of each memory cell. However, other factors, such as subthreshold leakage currents and alpha-particle induced soft errors, require that larger storage capacitors be used. Thus, there is a need in the art to increase memory density while allowing the use of storage capacitors that provide sufficient immunity to leakage currents and soft errors. There is also a need in the broader integrated circuit art for dense structures and fabrication techniques. There is a further need in the art to increase integrated circuit density while providing body bias voltage signals that are capable of improving the characteristics of both xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d access FET switching devices.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit including a pillar of semiconductor material that extends outwardly from a working surface of a substrate. The pillar has a number of sides. A transistor is formed having body and first and second source/drain regions within the pillar. The transistor includes a gate and a body contact that are each associated with a side of the pillar.
The invention also provides a memory device including an array of memory cells. Each cell includes a transistor. Each transistor includes a semiconductor pillar forming body and first and second source/drain regions. The transistor also includes a gate and a body contact disposed adjacent to opposing sides of the pillar. The memory device also includes a plurality of substantially parallel word lines. Each word line is disposed orthogonally to the bit lines in a trench between columns of the memory cells. Each word line allows addressing of gates of the transistors of the memory cells that are adjacent to the trench in which the word line is disposed The memory device also includes a plurality of substantially parallel body lines. The body lines are interdigitated with the word lines. Each body line is disposed orthogonally to the bit lines in a trench between columns of the memory cells. Each body line provides a signal to body regions of the transistors of the memory cells that are adjacent to the trench in which the body line is disposed. A plurality of bit lines is provided, proximal to the substrate. The bit lines interconnect ones of the first source/drain regions of ones of the memory cells. In one embodiment, the pillars extend outwardly from an insulating portion of the substrate. In another embodiment, the pillars extend outwardly from a semiconductor portion of the substrate.
The invention also provides a method of fabricating an integrated circuit. According to one embodiment of the method, a substrate is provided, and a plurality of bit lines are formed on the substrate. A plurality of access transistors are formed on each of the bit lines. Each access transistor includes a first source/drain region shared by at least a portion of the bit line. Each access transistor also includes a body region and second source/drain region formed vertically on the first source/drain region. A plurality of isolation trenches are formed in the substrate, orthogonal to the bit lines. Each trench is located between access transistors on the orthogonal bit lines. A word line is formed in a first one of the trenches. The word line controls conduction between first and second source/drain regions of access transistors that are adjacent to a first side of the first trench A body line is formed in a second one of the trenches. The body line interconnects body regions of access transistors that are adjacent to a first side of the second trench.
In one embodiment, the word line also controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the first trench. In another embodiment, the body line also interconnects body regions of access transistors that are adjacent to a second side of the second trench.
In a further embodiment, another word line is formed in the first trench, for controlling conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the first trench. In yet a further embodiment, another body line is formed in the second trench, which interconnects body regions of access transistors that are adjacent to a second side of the second trench.
Thus, the invention provides high density integrated circuit structures and fabrication methods, such as for DRAM memory cell arrays and other semiconductor devices. One aspect of the invention allows for buried bit, word, and body lines, providing high integration density. Each memory cell can be fabricated in a surface area that is approximately 4F2, where F is a minimum lithographic feature size. In one embodiment, a common word line is shared by all of the access FETs that are located along both sides of the trench in which the word line is located. In another embodiment, a common body line is shared by all of the access FETs that are located along both sides of the trench in which the body line is located. In a further embodiment, split word lines are provided in first alternating trenches, and the split word lines provide separate addressing of gate regions of access FETs on opposite sides of the trench. In yet a further embodiment, split body lines are provided in second alternating trenches, and the split body lines provide separate interconnection of body contacts to body regions of the access FETs on opposite sides of the trench. Each of the unitary and split word and body line embodiments can be fabricated on a bulk semiconductor substrate, or on a semiconductor-on-insulator (SOI) substrate that results from using an SOI starting material, or by forming SOI regions during fabrication. The SOI embodiments provide greater immunity to alpha-particle induced soft errors, allowing the use of smaller storage capacitors.